Hardware Optimization and Implementation of a 16-Channel Neural Tree Classifier for On-Chip Closed-Loop Neuromodulation

Abstract

This work presents the development of on-chip machine learning (ML) classifiers for implantable neuromodulation system-on-chips (SoCs), aimed at detecting epileptic seizures for closed-loop neuromodulation applications. Tree-based classifiers have gained prominence due to low on-chip memory requirements for binary classification. This work focuses on optimizing hardware performance and associated trade-offs from two fronts, namely, (a) implementation of the Neural Tree (NT) classifier using model compression techniques and (b) design of feature extraction engine (FEE) using FIR filters and time-division multiplexed hardware optimizations. We provide insights into how model compression techniques of Neural Networks like weight pruning and weight sharing can be exploited to reduce the memory requirement of Neural Tree inference hardware. Both these techniques effectively reduce non-zero weights and therefore help to reduce memory requirements. We also detail the choice of feature extraction engine (FEE) hardware to extract temporal and spectral features and the relevant area-power-attenuation trade-offs for spectral feature extraction. The end-to-end hardware comprising the FEE, the Neural Tree classifier and serial peripherals are tested on a Zynq-7000 series SoC using pre-recorded patient data. The SoC-based evaluation platform allows rapid testing of various model optimizations on hardware using AXI protocol. The entire system, trained on data from the CHB-MIT scalp EEG database, achieved a sensitivity of 95.7% and a specificity of 94.3%, with an on-chip memory of 0.59 kB. Implementing the design in a 65nm CMOS process resulted in a worst-case power of 174 $\mu$W and an area of 0.16 mm${}^{2}$. These findings along with the optimizations mark significant progress toward energy-efficient, scalable neuromodulation systems capable of real-time neurological disorder prediction.