Xianhu Luo;Xu Cheng;Jiangan Han;Weikang Zhou;Yunbo Rao;Liang Zhang;Fengjun Chen;Binbin Cheng;Xianjin Deng
{"title":"A D-Band ×8 Frequency Multiplier With Harmonic Suppression Enhancements in SiGe BiCMOS","authors":"Xianhu Luo;Xu Cheng;Jiangan Han;Weikang Zhou;Yunbo Rao;Liang Zhang;Fengjun Chen;Binbin Cheng;Xianjin Deng","doi":"10.1109/LMWT.2024.3515486","DOIUrl":null,"url":null,"abstract":"In this letter, a D-band frequency octupler (<inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula>) with high harmonic suppression is presented in a 0.13-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m SiGe BiCMOS technology. To enhance the suppression of even harmonics among high harmonics, we have implemented and refined a waveform shaping technique that effectively elevates the second harmonic while suppressing the fourth, sixth, and higher even harmonics. Additionally, the transformer-based bandpass filters (BPFs) are integrated into the design of the <inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula> frequency multiplier to enhance the suppression of nontarget frequency signals without compromising power consumption. To validate our proposed concept, a D-band <inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula> frequency multiplier operating at 114.5–140 GHz is manufactured in a SiGe process. The circuit achieved an output power of −2.5 dBm with an input power of −2 dBm. Within the 3-dB bandwidth, the suppression of various harmonics exceeded 28 dBc and with the maximum suppression exceeding 38 dBc. The chip consumed 125 mW of power and occupied an area of <inline-formula> <tex-math>$0.63\\times 1.2$ </tex-math></inline-formula> mm2.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 3","pages":"314-317"},"PeriodicalIF":0.0000,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10829964/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this letter, a D-band frequency octupler ($\times 8$ ) with high harmonic suppression is presented in a 0.13-$\mu $ m SiGe BiCMOS technology. To enhance the suppression of even harmonics among high harmonics, we have implemented and refined a waveform shaping technique that effectively elevates the second harmonic while suppressing the fourth, sixth, and higher even harmonics. Additionally, the transformer-based bandpass filters (BPFs) are integrated into the design of the $\times 8$ frequency multiplier to enhance the suppression of nontarget frequency signals without compromising power consumption. To validate our proposed concept, a D-band $\times 8$ frequency multiplier operating at 114.5–140 GHz is manufactured in a SiGe process. The circuit achieved an output power of −2.5 dBm with an input power of −2 dBm. Within the 3-dB bandwidth, the suppression of various harmonics exceeded 28 dBc and with the maximum suppression exceeding 38 dBc. The chip consumed 125 mW of power and occupied an area of $0.63\times 1.2$ mm2.