A High-Efficiency 485–525 GHz On-Chip Power Combining Tripler Using Three-Port Matching Technology

Abstract

In this letter, a high-efficiency 485–525 GHz frequency balanced tripler using three-port matching technology (TPMT) is reported. In comparison to traditional balanced tripler, the TPMT uses an on-chip capacitor connected to a biased microstrip line (Ms) at the bias port, which not only provides dc and RF isolation but also functions as part of the diode matching. The impedance of bias port participates in the matching process of the diode, effectively reducing the parasitic effect associated with the on-chip capacitance and thereby enhancing the efficiency of the tripler. In addition, this study adopts the on-chip power combining technology to improve the power handling capability of the frequency tripler and minimize the effects of assembly errors. At room temperature, the measured results show that the tripler has an efficiency of 4.2%–13.42% over the 485–525 GHz band at 70–172-mW input power.