A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

Abstract

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss and crosstalk at the Nyquist frequency are −2.4 and −18.1 dB, respectively. The receiver (RX) includes real-time clock data recovery (CDR) and a bathtub monitor for each lane, optimizing sampling point adjustments and tracking phase drift across voltage and temperature variations. With all lanes active, the physical layer (PHY) achieves a density of 3.84 Tb/s/mm and operates with a power consumption of 0.36 pJ/bit. The worst-performing lane shows a 0.342 UI opening at a bit error rate (BER) of 1e⁻¹², and an interpolated 0.331 UI opening at a BER of 1e⁻¹⁵ when running at 32 Gb/s. Additionally, results for 25 Gb/s operation are included as a lower power alternative. This article will discuss the design details and trade-offs of the transceiver.