Optimization of pocket doped SOI TFET and analysis of interfacial trap charges

Abstract

This paper investigates the optimization of various parameters in the design of silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) with pocket doping (PD-SOI TFET). By performing comprehensive simulations using Sentaurus TCAD and incorporating appropriate models, we systematically studied the effects of optimizing channel length (L_CH), channel thickness (t_CH), oxide thickness (t_ox), pocket doping length (L_PD), pocket doping material (PD_m), and source/channel material. Our results show that there is an optimal design parameter for a channel length of 40 nm, a channel thickness of 10 nm, an oxide thickness of 2 nm, a pocket doping length of 2 nm, and the pocket doping material like germanium (Ge). Using Si as the source and Ge as the channel material, the device shows better performance. Additionally, the optimized PD-SOI TFET's interface trap charges have been studied. The existence of interface traps has an impact on the device's performance. In comparison to negative ITCs, positive ITCs provide higher electron band-to-band generation rate (eBTBT). For positive ITCs, the electric field yields larger values in the normal component, and for negative ITCs, higher values in the parallel component. The subthreshold slope degrades for positive ITCs and slightly reduces for negative ITCs. Further, the device’s performance is analyzed through studying the impact of interface traps on various analog/RF parameters including the Total gate capacitance (C_gg), Gate to source capacitance (C_gs), Gate to drain capacitance (C_gd), transconductance (g_m), and cut-off frequency (f_T). Also, the linearity and distortion parameters have been analyzed in form of VIP2, VIP3, IIP3 and IMD3.