Device and circuit-level assessment of temperature variation on the DC, Analog/RF and linearity performance metrics of III-V TFETs for reliability

Abstract

This article presents a comprehensive comparative analysis of GaSb/Si Dual Material Stacked Double Gate Hetero Junction TFET (GaSb/Si DMSDG HJTFET) and $G{a}_{0.5}$ $A{s}_{0.5}$Sb/$I{n}_{0.7}$ $G{a}_{0.3}$As Ferroelectric Dual Material Stacked Double Gate Hetero Junction TFET (FDMSDG-HJTFET) at device-level as well as circuit-level under the influence of temperature variation for the first time. In this work, the effects of temperature variation in the range of 300 K to 420 K have been accounted. Here, the DC electrical parameters, analog/RF and linearity parameters of both devices have been investigated using Silvaco TCAD tool. Further, the impact of temperature variation on the performance at the circuit level is carried out through a resistive-load inverter with GaSb/Si DMSDG-HJTFET and FDMSDG-HJTFET, evaluating their DC and transient characteristics using HSPICE. The simulation results reveal that the FDMSDG-HJTFET device is more immune to temperature variations, in contrast to GaSb/Si DMSDG-HJTFET. Thus, it can be utilized for low-power, analog/RF and high-temperature applications.