Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application

Abstract

This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g_m over I_d (g_m/I_d) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).