A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-02-27 DOI:10.1016/j.mejo.2025.106612

Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

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引用次数: 0

Abstract

High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.