Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue
{"title":"Garbage collection optimization with data separation for large data storage in deep learning applications","authors":"Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue","doi":"10.1016/j.mejo.2025.106620","DOIUrl":null,"url":null,"abstract":"<div><div>Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106620"},"PeriodicalIF":1.9000,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125000694","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.