A new power-rail clamp circuit for on-chip electrostatic discharge protection

Abstract

Power-rail clamp circuit is crucial for the whole-chip electrostatic discharge (ESD) protection. In this paper, a new power-rail clamp circuit for on-chip ESD protection is proposed and verified by silicon. A dedicated false-triggering suppression circuit is introduced to make sure that the proposed clamp circuit keeps off during fast power-up events. By skillfully incorporating slew rate and voltage detection mechanisms are, offering a low clamp voltage and a reliable turn-off functionality. Experimental results from fabricated silicon die verify that the proposed clamp circuit exhibits high immunity to false triggering, making it suitable for robust ESD protection. Comparisons with the traditional solution are also presented.