A power-efficient spiking convolutional neural network accelerator based on temporal parallelism and streaming dataflow

Abstract

The spiking convolutional neural network (SCNN) accelerator is well-suited for intelligent edge devices due to its low power consumption. However, there is still room for improvement in its power efficiency, particularly in terms of computation and memory optimization. In this paper, a temporal parallelism method is proposed to enhance power efficiency by minimizing unnecessary data movement. A streaming dataflow mechanism is introduced to pipeline the computations of convolution and pooling layers. Additionally, a configurable decomposition technique is designed to support arbitrary kernel sizes. The proposed accelerator is implemented on a Xilinx ZCU102 FPGA development board with a clock frequency of 200 MHz. Experiment results show that the proposed design consumes only 1.69 W of power while achieving a peak performance of 921.6 GOPS, resulting in a power efficiency of 545 GOPS per watt.