Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF

Abstract

Random Number Generators (RNGs) are pivotal in cryptographic applications, safeguarding the security and confidentiality of sensitive data through the generation of unpredictable cryptographic keys. Static Random Access Memory (SRAM)-based Physical Unclonable Functions (PUFs) offer a low-overhead alternative for generating randomness in Hybrid Random Number generator (HRNG) architectures, leveraging minimal hardware resources while maintaining robust performance. The proposed work presents a novel HRNG design that leverages an SRAM-based PUF as the entropy source. The extracted SRAM data undergoes a robust post-processing scheme involving a specialized one-way hash function, enhancing the randomness and unpredictability of the generated sequences. The HRNG architecture is implemented on Intel Cyclone IV E FPGA, which utilized 779 logic elements to achieve a throughput of 102.421 Mbps while consuming 148.02 mW of power dissipation to produce 2²³ bits. The performance was rigorously evaluated through NIST SP 800–22 test batteries that has 99.9% of pass rate, entropy analysis ensuring equidistribution, hamming distance, and correlation assessments. Compared to the state-of-the-art RNGs such as memristor chaos, metastable circuits, chaotic oscillators, the proposed method shows its efficacy in eliminating large hardware dependency while yielding robust randomness. Operating at 50 MHz, the proposed HRNG achieves a competitive balance between performance and power consumption, with a throughput that surpasses many existing implementations.