Parasitic-induced multi-zero generation and port-fusion compact filter based on 3-D through-silicon via technology

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Xiangkun Yin, Xiangyu Ma, Nairong Liu, Libo Qian, Tao Zhang, Qijun Lu, Zhangming Zhu
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引用次数: 0

Abstract

A approach to achieving compactness and performance enhancement in lowpass filter (LPF) is described in this work. By leveraging the parasitic inductance of metal interconnects as inductive components, the proposed approach significantly reduces the overall size of the filter. Additionally, the combined effect of parasitic inductance and source-load coupling parasitic capacitance is utilized to create multiple transmission zeros, leading to improved isolation and wider bandwidth. Furthermore, a port fusion technique is introduced, which reduces the number of ports, minimizing interconnect losses and further enhancing compactness. The proposed LPF occupies a compact space of 0.31 × 0.34 mm2, features a cut-off frequency of 6.31 GHz, achieves an insertion loss of 30 dB at 30 GHz, and maintains a return loss below 0.4 dB.
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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