An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process

IF 4.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-02-27 DOI:10.1109/JSSC.2025.3541174

Fabio Giunco;Marco Sosio;Claudio Nani;Ivan Fabiano;Travis Lovitt;Victor Karam;Domenico Albano;Claudio Asero;Nicola Codega;Marco Garampazzi;Nicola Ghittori;Leonardo Daniel Herbas Burgos;Stanley S. K. Ho;Enrico Monaco;B. Reyes;P. Rossi;Enrico Temporiti;Paolo Pascale;Fernando De Bernardinis;Shawn Scouten;Stephen Jantzi

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引用次数: 0

Abstract

In this article, we present an eight-lane 800-Gb/s transceiver, which enables the implementation of pluggable optical modules with pulse amplitude modulation (PAM)-4 modulation and direct detection. The transceiver features a host interface composed of eight TX and RX lanes compliant with the optical internetworking forum (OIF) common electrical I/O (CEI) 112G very short reach (VSR) and IEEE 802.3 chip to module (C2M) standards and integrates eight TX and RX lanes on the optical (line) side. Three fully integrated high-voltage optical TXs have been integrated with minimum area and power overhead by changing only few top metal masks: 3-Vpp silicon photonics (SiPho), 3-V open drain (OD), and 1.5-Vpp electro absorption modulated laser (EML) driver. External additional drivers suitable, e.g., for vertical cavity surface emitting laser (VCSEL) applications are supported by exploiting optical driver software reconfigurability into standard driver mode. The optical RXs, identical for all the applications, are digital signal processing (DSP) based, with the analog section consisting of a variable gain amplifier (VGA) and an analog-to-digital converter (ADC). The VGA can be dc coupled to an external trans-impedance amplifier (TIA) without the need for external components. The chip is implemented in 5-nm FinFET technology and it is designed to deliver the target performance both in package and bare die. Both versions meet the form factor and power requirements for quad small form factor pluggable double density (QSFP-DD) multi-source agreement (MSA) specifications and are suitable for optical interconnects covering most of the optical standards such as DR8/2xFR4/LR8/SR8.

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用于5纳米FinFET工艺PAM-4光直接检测的8通道800 gb /s收发器

在本文中，我们提出了一个8通道800 gb /s收发器，它可以实现具有脉冲幅度调制(PAM)-4调制和直接检测的可插拔光模块。该收发器具有由8个TX和RX通道组成的主机接口，符合光互连论坛（OIF）通用电气I/O (CEI) 112G极短距离（VSR）和IEEE 802.3芯片到模块（C2M）标准，并在光（线）侧集成了8个TX和RX通道。三种完全集成的高压光学TXs通过更换几个顶部金属掩模，以最小的面积和功率开销集成：3-Vpp硅光子（SiPho）， 3-V开漏（OD）和1.5 vpp电吸收调制激光（EML）驱动器。通过利用光驱动软件可重构性进入标准驱动模式，支持适用于垂直腔面发射激光器（VCSEL）应用的外部附加驱动器。光学rx适用于所有应用，基于数字信号处理（DSP），模拟部分由可变增益放大器（VGA）和模数转换器（ADC）组成。VGA可以直流耦合到外部跨阻抗放大器（TIA），而不需要外部组件。该芯片采用5nm FinFET技术，旨在实现封装和裸晶片的目标性能。两种版本均满足四极QSFP-DD （small form factor pluggable double density）多源协议（multi-source agreement， MSA）规格的外形尺寸和功耗要求，适用于DR8/2xFR4/LR8/SR8等大多数光标准的光互连。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.