Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction

Abstract

This brief analyzes the phase noise (PN) and reference (REF) spur performance of the reference-sampling (RS) PLL when the total sampling capacitor $(C_{\mathrm { S}})$ is reduced to save the power consumption of the crystal oscillator (XO) buffer. Based on the analysis, the saved power consumption from the XO buffer can be utilized to improve the PN of the voltage-controlled oscillator (VCO), which compensates for the in-band PN degradation induced by the $C_{\mathrm { S}}$ reduction. Based on this theme, we can reduce the total power consumption of the RS-PLL and the XO buffer without degrading the output root-mean-square (RMS) jitter by reducing $C_{\mathrm { S}}$ if a VCO with a high figure-of-merit (FoM) and a low $1/{f}^{3}$ PN corner frequency is available. A type-II RS-PLL prototype utilizing a gain-boosting RS phase detector to suppress the voltage-to-current $(G_{\mathrm { M}})$ circuit noise is designed to verify the presented design strategy. With the aid of an inverse-class-F VCO with a FoM of 190.4 dBc/Hz at 1 MHz offset frequency and a $1/{f}^{3}$ PN corner frequency of 300 kHz across the frequency tuning range from 5.2 GHz to 6.1 GHz, the RS-PLL prototype fabricated in a 65-nm CMOS achieves low RMS jitter and REF spur of 64.8 fs and -84.1 dBc, respectively, while dissipating 6.9 mW, corresponding to a jitter-power FoM ( $\rm FoM{_{J}}$ ) of -255.4 dB.