On the Effect of Memory Error in a Time-Interleaved Pipeline ADC With a Shared Residue Amplifier

Abstract

Compared to traditional time-interleaved (TI) pipeline ADC, shared residue amplifier (RA) architecture is potentially more power efficient and requires simpler calibration. However, the shared RA architecture suffers from memory error, which severely degrades its linearity. Typically, a reset phase is needed at the RA’s input to avoid this memory error. The reset phase is particularly problematic for high-speed ADCs as it shortens the amplification time, leading to higher power consumption in the RA. This brief analyzes the effect of memory error and presents a simple digital memory correction technique for a reset-free and shared open-loop based pipeline ADC. A 14-bit TI pipeline-SAR ADC, running at 2 GS/s, is designed and fabricated to verify the proposed analysis and correction method. Experimental results show improvements of upto 5.1 dB in the signal-to-noise-and-distortion ratio (SNDR) and more than two times in the integral nonlinearity (INL) with the proposed digital memory correction technique.