Humidity and ring spacing variation tolerant design of a SiC power MOSFET using mirrored floating field rings

Abstract

Prior designs of the number and spacing of the Floating Field Rings (FFRs) in the edge termination of SiC MOS-FETs have limitations. They neglect the possible degradation of the breakdown voltage, V_BR, due to two reasons: (1) widening, α, of the ring due to lateral straggle of dopants during implant-action, and over-etching of the window during the prior lithography step; (2) presence of a negative SiC/SiO₂ interface charge, Q_H, over a part or whole of the edge termination length due to migration of aluminates formed from reaction of the gate metal with humidity in the environment. We propose an improved algorithm to design a FFR structure considering α. Further, we show that by extending this structure by its mirrored version, we get what we call a Mirrored FFR (MFFR) structure, which is tolerant to Q_H as well as α. The concept is illustrated using well calibrated TCAD simulations of a 600 V SiC MOSFET with α = 0.3 μm and Q_H = − 3 × 10¹² cm⁻²; the V_BR with prior FFR designs degraded by up to 48 % while that with MFFR design by just 16 %. Thus, MFFR structure yields a device with the least overhead factor of V_BR, that in turn allows realization of a lower specific on-resistance.