A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits

Abstract

This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation architecture with an integrating receiver. The homodyne receiver module for each qubit employs a dedicated local LO generator for a coherent detection under a frequency-division multiplexed multi-qubit readout environment. To mitigate the conventional issues of the homodyne demodulation in wireless communications, such as 1/f noise and DC offset by LO leakage, the proposed receiver incorporates effective calibration schemes by utilizing the specific operating conditions of the superconducting qubits. The implemented chip in 40 nm CMOS is tested at 4 K in a dilution refrigerator under an emulated SNR environment of superconducting qubit readout, i.e. -70 dBm input with a noise floor of -148 dBm/Hz. Measurement shows that circuit-only fidelity reaches 99% in 200 ns with an ideal single tone RF input. A back-to-back test using an on-chip 4-tone transmitter shows a 93 % circuit-only fidelity with 400 ns integration.