{"title":"A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation","authors":"Shan Cao;Shan Chen;Limin Jiang;Zhiyuan Jiang","doi":"10.1109/TCSI.2024.3485634","DOIUrl":null,"url":null,"abstract":"With the evolution of wireless communication systems, there is a growing demand for high reliability and low latency in channel coding, particularly in 5G and beyond wireless systems used in applications such as autonomous driving and remote medical services. For the decoding of polar codes, the multi-bit successive cancellation list (MSCL) decoding technique was recently introduced to decrease the decoding latency by decoding several short inner codes in parallel, which preserves high reliability compared to the conventional successive cancellation list (SCL) decoding. However, as parallelism increases, the complexity of the decoding path sorting also increases significantly, which makes it resource-intensive for hardware implementation. To address this issue, this paper proposes a configurable critical-set-based multi-bit successive cancellation list (CS-MSCL) decoding algorithm, which first introduces critical sets to the MSCL decoding for the optimization of path pruning. Subsequently, an enhanced CS-MSCL algorithm is introduced for large list-size MSCL decoding, which can boost the error correction performance. Then, an area-efficient decoding architecture is introduced, which supports the cyclic redundancy check (CRC) and the CS-MSCL decoding compatible with the 5G standard. The proposed decoder is implemented in SMIC 40 nm CMOS technology with a parallelism degree of 8, which has a peak area efficiency of <inline-formula> <tex-math>$4.64~\\mathrm {Gbps/mm^{2}}$ </tex-math></inline-formula> for list size 4 and <inline-formula> <tex-math>$2.01~\\mathrm {Gbps/mm^{2}}$ </tex-math></inline-formula> for list size 8. Compared to state-of-the-art SCL-based decoders, the normalized area efficiency is improved by 7.16% and 17.54% for list sizes 4 and 8, respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 3","pages":"1472-1485"},"PeriodicalIF":5.2000,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems I: Regular Papers","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10738838/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
With the evolution of wireless communication systems, there is a growing demand for high reliability and low latency in channel coding, particularly in 5G and beyond wireless systems used in applications such as autonomous driving and remote medical services. For the decoding of polar codes, the multi-bit successive cancellation list (MSCL) decoding technique was recently introduced to decrease the decoding latency by decoding several short inner codes in parallel, which preserves high reliability compared to the conventional successive cancellation list (SCL) decoding. However, as parallelism increases, the complexity of the decoding path sorting also increases significantly, which makes it resource-intensive for hardware implementation. To address this issue, this paper proposes a configurable critical-set-based multi-bit successive cancellation list (CS-MSCL) decoding algorithm, which first introduces critical sets to the MSCL decoding for the optimization of path pruning. Subsequently, an enhanced CS-MSCL algorithm is introduced for large list-size MSCL decoding, which can boost the error correction performance. Then, an area-efficient decoding architecture is introduced, which supports the cyclic redundancy check (CRC) and the CS-MSCL decoding compatible with the 5G standard. The proposed decoder is implemented in SMIC 40 nm CMOS technology with a parallelism degree of 8, which has a peak area efficiency of $4.64~\mathrm {Gbps/mm^{2}}$ for list size 4 and $2.01~\mathrm {Gbps/mm^{2}}$ for list size 8. Compared to state-of-the-art SCL-based decoders, the normalized area efficiency is improved by 7.16% and 17.54% for list sizes 4 and 8, respectively.
期刊介绍:
TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.