Detection and Mitigation of nBTI Aging of a High Precision Current Comparator in 16 nm FinFET Technology

Abstract

Aging effects in deep sub-micron CMOS have become significant design challenges, particularly in precision analog circuits, not only due to the inaccuracy of aging modeling and simulators, but also a lack of detection methods incorporated into problematic silicon. In this work, we introduce a detection method to sense aging-related degradations in a precision current comparator, fabricated in 16nm FinFET technology. Utilizing this method we found that nBTI aging-related degradation results in a time-varying and memory-dependent hysteresis in the comparator. We propose two different mitigation methods: stress-balance and clamp diode attenuation schemes. The stress-balance mitigation scheme helps to balance any residual aging-related hysteresis on the comparator, whereas the clamp diode attenuation scheme reduces the aging-related degradation. Finally, the proposed aging-related mitigation schemes have been verified with silicon measurement data.