Recoding Hybrid Stochastic Numbers for Preventing Bit Width Accumulation and Fault Tolerance

Abstract

Stochastic computing is a promising technique for realizing high-performance computing owing to its extremely low hardware cost. However, the stochastic number (SN) has too many information redundancies, which leads to an exponential growth of latency. So, hybrid stochastic number (HSN) is proposed to solve the high-latency problem. Hybrid stochastic computing technology brings latency and efficiency advantages but faces the rigorous challenges of bit-width accumulation. In this study, a recoding method with high accuracy for HSN is proposed to reduce the bit width of HSN with only one clock delay. The hardware-resource savings in the polynomial circuit reach more than 80%. Then, the accuracy and fault tolerance of recoding are evaluated. The recoding method enables the pipeline structure in the pure HSN domain, preventing data conversion at the midpoint of the computation. Furthermore, based on the recoding method, a low-cost, bit-flip correction method for HSN is proposed, for realizing fault-tolerant data transmission and computation.