Reducing delay and resistance of GNR based interconnect using insertion of buffers

Abstract

As devices get extremely miniaturized at deep sub-micron design levels, the interconnections between logic blocks significantly influence the overall delay, power dissipation, and area of the system. Surface and grain-boundary scattering, high mobility degradation, higher leakage power, and considerable dopant variation as a result of continuous scaling all contribute to a rise in interconnect resistivity. Due to the superior electrical, mechanical, and thermal properties of graphene nanoribbon (GNR) material, GNR-interconnects may be viable substitutes for copper in future interconnects. Unlike traditional copper-interconnect, the routing in GNR-intrconnect is different. Recently routing with GNR-interconnect have been studied in different literatures with the objectives to reduce interconnect delay and resistance. In order to cope with the system of high speed and less area, interconnect-delay and resistance are needed to be further optimized. In this paper we discuss the issue of insertion of buffers in GNR-interconnect and show that proper insertion of buffers in GNR-interconnect may decrease both interconnect delay and resistance significantly. Whereas in traditional copper-interconnect only delay is reduced by insertion of buffers. We also discuss that the signal and power integrity as well as the stability also improve with the insertion of buffers. We propose an algorithm for proper insertion of buffers to decrease both of them. Elmore delay model is used to compute the delay of GNR interconnects. We observe the minimum 30% and 40% reduction in the interconnect resistance and the interconnect delay respectively in all test cases. The computational worst case time complexity of the algorithm proposed in this manuscript is \({\mathcal {O}}({n^3})\), where n is the number of terminals in the routing.