An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion

Abstract

The increase in performance promised by the recent generation of double data rate (DDR) memory, DDR5, is conditioned by addressing its signal integrity challenges. The DDR5 standard specifies a 4-tap decision feedback equalizer (DFE) at the memory receiver to deal with these challenges. Although adaptive equalization is a mature field, known methods for DFE calibration are limited by the DDR5 interface complexity and the equalization requirements mandated by its specification. In this article, we propose a novel approach based on linear inversion of channel stimulus that leverages specific architectural details of DDR5 and can tune memory devices deterministically at runtime. In addition to using few hardware resources relative to a modern memory controller, by operating at very low latency, this new approach facilitates periodic equalization when the DFE is offline, thus avoiding DFE error propagation during training inherent to adaptive techniques.