An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-04 DOI:10.1109/TVLSI.2024.3505835

Mitchell Cooke;Nicola Nicolici

引用次数: 0

Abstract

The increase in performance promised by the recent generation of double data rate (DDR) memory, DDR5, is conditioned by addressing its signal integrity challenges. The DDR5 standard specifies a 4-tap decision feedback equalizer (DFE) at the memory receiver to deal with these challenges. Although adaptive equalization is a mature field, known methods for DFE calibration are limited by the DDR5 interface complexity and the equalization requirements mandated by its specification. In this article, we propose a novel approach based on linear inversion of channel stimulus that leverages specific architectural details of DDR5 and can tune memory devices deterministically at runtime. In addition to using few hardware resources relative to a modern memory controller, by operating at very low latency, this new approach facilitates periodic equalization when the DFE is offline, thus avoiding DFE error propagation during training inherent to adaptive techniques.

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一种基于通道刺激反演的DDR5 DFE标定嵌入式架构

最新一代双数据速率（DDR）内存DDR5所承诺的性能提升，是以解决其信号完整性挑战为条件的。DDR5标准在内存接收器上指定了一个4分路决策反馈均衡器（DFE）来处理这些挑战。虽然自适应均衡是一个成熟的领域，但已知的DFE校准方法受到DDR5接口复杂性和其规范规定的均衡要求的限制。在本文中，我们提出了一种基于通道刺激线性反演的新方法，该方法利用了DDR5的特定架构细节，可以在运行时对内存设备进行确定性调优。除了相对于现代内存控制器使用很少的硬件资源之外，通过以非常低的延迟操作，这种新方法有助于在DFE离线时进行周期性均衡，从而避免了自适应技术固有的训练期间DFE错误传播。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.