A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS

Abstract

A fourth-order continuous-time (CT) sigma-delta modulator (SDM) is presented for RF front-end system-on-chip (SoC) applications. Due to system constraints, only a 1 V power supply is available. To address this, we propose a three-stage operational amplifier with feedforward compensation that operates efficiently at low voltage. This amplifier achieves a DC gain of 78.5 dB and maintains a gain of 53.4 dB at an input signal frequency of 100 MHz, with a unity gain bandwidth of only 4.2 GHz. In contrast, traditional Miller-compensated operational amplifiers would require a unity gain bandwidth as high as 40.7 GHz to achieve similar performance. To mitigate DAC unit cell mismatch, we propose a dynamic element matching (DEM) circuit implementation utilizing a data-weighted averaging (DWA) algorithm. By removing the DEM block from the loop, the delay of this block does not affect the delay of the loop filter. This DEM technique enhances the signal-to-noise and distortion ratio (SNDR) by 13.9 dB and the spurious-free dynamic range (SFDR) by 20 dB. The prototype, implemented using a 28 nm CMOS process, achieves a dynamic range (DR) of 73.7 dB and a peak SNDR of 66.8 dB.