Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging

Abstract

Conventional successive approximation register (SAR) ADCs encounter a compromise between accuracy and power consumption. This work presents an efficient noise-reduction scheme to mitigate sampling noise and comparator noise. The kT/C noise cancellation technique reduces the kT/C noise and facilitates the reduction of the sampling capacitance to one-sixth of its typical value in conventional architectures. LSB repeating and adaptive tracking averaging(ATA) technique are also employed to decouple the correlation between the energy and the noise in the comparator. Post-simulation results indicate that the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the proposed 14-bit prototype SAR ADC attain values of 84.5 dB and 95.5 dB respectively at a Nyquist input rate and a sampling rate of 1 MS/s. The power consumption is 431.6 $\mu$W with a 1.8 V power supply, resulting in a “Walden” figure of merit (FoMw) of 35.7 fJ/conv-step and a “Schreier” figure of merit (FoMs) of 173.3 dB in a 0.18-$\mu$m CMOS process.