This research presents the design of a CMOS cascode operational amplifier with a common source and common drain configuration for an instrumentation amplifier (INA) that has been optimised to operate at 1 V. Three distinct instrumentation amplifiers with three separate topologies have been designed to increase gain accuracy and high common-mode rejection ratio (CMRR) while reducing power dissipation. The three operational amplifier (Op-amps) topologies such as a single-stage operational amplifier, folded cascode operational amplifier, and multistage operational amplifier have been designed in which biasing is provided using the voltage divider technique and we obtained high gain and high CMRR, and low-power consumption. The aspect ratio plays an important role. The three Op-amp based INAs were constructed, and a separate comparison was made utilising these Op-amp topologies. The multistage INA has attained 124.323dB gain and 130.465 dB CMRR with a 99.7% gain accuracy. To visualize the effectiveness of the proposed design, we have done a comparative analysis with prior work. Utilising Cadence’s Virtuoso environment UMC 90 nm CMOS Technology, simulations of operational amplifiers and INAs were carried out.