A novel design of CMOS Cascode operational amplifier based Instrumentation amplifiers for high gain, CMRR, and low power dissipation

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Divya Sharma, Vijay Nath
{"title":"A novel design of CMOS Cascode operational amplifier based Instrumentation amplifiers for high gain, CMRR, and low power dissipation","authors":"Divya Sharma,&nbsp;Vijay Nath","doi":"10.1007/s10470-025-02349-5","DOIUrl":null,"url":null,"abstract":"<div><p>This research presents the design of a CMOS cascode operational amplifier with a common source and common drain configuration for an instrumentation amplifier (INA) that has been optimised to operate at 1 V. Three distinct instrumentation amplifiers with three separate topologies have been designed to increase gain accuracy and high common-mode rejection ratio (CMRR) while reducing power dissipation. The three operational amplifier (Op-amps) topologies such as a single-stage operational amplifier, folded cascode operational amplifier, and multistage operational amplifier have been designed in which biasing is provided using the voltage divider technique and we obtained high gain and high CMRR, and low-power consumption. The aspect ratio plays an important role. The three Op-amp based INAs were constructed, and a separate comparison was made utilising these Op-amp topologies. The multistage INA has attained 124.323dB gain and 130.465 dB CMRR with a 99.7% gain accuracy. To visualize the effectiveness of the proposed design, we have done a comparative analysis with prior work. Utilising Cadence’s Virtuoso environment UMC 90 nm CMOS Technology, simulations of operational amplifiers and INAs were carried out.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 3","pages":""},"PeriodicalIF":1.2000,"publicationDate":"2025-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02349-5","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

This research presents the design of a CMOS cascode operational amplifier with a common source and common drain configuration for an instrumentation amplifier (INA) that has been optimised to operate at 1 V. Three distinct instrumentation amplifiers with three separate topologies have been designed to increase gain accuracy and high common-mode rejection ratio (CMRR) while reducing power dissipation. The three operational amplifier (Op-amps) topologies such as a single-stage operational amplifier, folded cascode operational amplifier, and multistage operational amplifier have been designed in which biasing is provided using the voltage divider technique and we obtained high gain and high CMRR, and low-power consumption. The aspect ratio plays an important role. The three Op-amp based INAs were constructed, and a separate comparison was made utilising these Op-amp topologies. The multistage INA has attained 124.323dB gain and 130.465 dB CMRR with a 99.7% gain accuracy. To visualize the effectiveness of the proposed design, we have done a comparative analysis with prior work. Utilising Cadence’s Virtuoso environment UMC 90 nm CMOS Technology, simulations of operational amplifiers and INAs were carried out.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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