A 6.5-GHz Power-Efficient Two-Stage Feedforward Self-Interference Cancellation Receiver

Abstract

This letter presents a two-stage feedforward (FF) power-efficient self-interference cancellation (SIC) frequency-division duplex (FDD) receiver at the 6.5-GHz band for 5G deployment. The first stage employs a transformer-feedback low-noise amplifier (LNA) that effectively reduces additional noise sources from the subsequent SIC stage, resulting in a low noise figure (NF) and low power consumption. In the second stage, the SIC path includes two passive mixers and a baseband variable gain amplifier (VGA) to attenuate the strong interfering signal from the transmitter. In addition, a passive-mixer-like transmission gate (PML-TG) is incorporated to ensure the synchronization of timing alignment between the main receiver path and the SIC path. Fabricated in a 0.18- $\mu $ m technology, this work demonstrates 25 dB of SIC at 200-MHz offset with a signal bandwidth of 160 MHz. The proposed circuit can operate at a transmitter interference level of up to 20 dBm while consuming only 23.8 mW of dc power.