A 112 dB SFDR 16-bit 1MS/s SAR ADC with an improved and robust analog self-calibration

Abstract

This paper introduces a highly linear 16-bit successive approximation register (SAR) ADC, featuring an improved and robust analog voltage calibration method. The proposed method precisely measures binary capacitor mismatch and redundant capacitor mismatch, enabling accurate compensation of mismatch error during normal operation. Both theoretical analysis and measurement results confirm that the proposed method can significantly improve ADC linearity and spectrum purity. Remarkably, the additional calibration capacitive digital-to-analog converter (CDAC) occupies only 5% of total CDAC area. The design, implemented in a 180-nm CMOS process, achieves an average spuriousfree dynamic range (SFDR) of 112 dB without employing any dynamic element matching (DEM) techniques and a signal-to-noise and distortion ratio (SNDR) of 92.6 dB. This prototype operating 3.3V power supply and 1MS/s sampling rate consumes 4.82 mW and achieves a figure of merit (FOM)s of 172.7 dB.