A 75.4–102.4-GHz Power Amplifier With 27.7−dB Gain and 16.9% PAE in 65-nm CMOS

Abstract

This letter presents a W-band wideband high-gain power amplifier (PA) with 65-nm CMOS technology. An inductor-series high-coupled transformer is proposed and combined with a weakly coupled transformer to form the hybrid interstage matching network, and thereby, the bandwidth of the four-stage PA is extended by the proposed gain-complementary bandwidth extension technique. The proposed PA achieves a measured peak gain of 27.7 dB with a 3-dB bandwidth from 75.4 to 102.4 GHz. The saturated output power (Psat), 1-dB output compression point (OP1dB), and the peak power-added efficiency (PAE) are 12.5, 10.2 dBm, and 16.9%, respectively. The measurement results are in good agreement with the simulation results, and the core chip area of the proposed PA is $170\times 600~\mu $ m.