Exploration of low area-high speed by hybrid method of Radix-8 Booth encoding and Vedic multiplier

Abstract

As technological scalability reaches its limitations, novel techniques for computing efficiency have been explored. Three different, high-speed, low-area systems for multiplying two signed numbers were proposed. An innovative architecture was introduced by implementing both the techniques of Booth encoding and Vedic Multiplication sutras by improving the area and speed. Three different architectures of radix encoding (i.e.) Radix-8 with the Vedic multiplier are proposed in this paper. To examine the benefits of rapid arithmetic units, hybrid Booth encoding with Vedic multiplier (Urdhva Tiryakbhyam sutra) was implemented and simulated using Xilinx ISE 14.7 and Xilinx Vivado 2019.1 with FPGA and in ASIC 45 nm TSMC CMOS technology. The proposed design is found to have a high speed with minimal area consumption and includes a variety of cutting-edge architecture. For Hybrid Booth-Vedic-Radix-8 encoding (HBVR-8), the findings show that the proposed multiplier decreases area by 92.7%, 94.9%, and 95.4% for the three proposed architectures. The Area-Delay Product (ADP) was reduced by 1%, 41% and 51% for all three proposed architectures. The findings show that the provided method works better than the alternatives previously offered in the literature, despite the reached configurability and affordable design.