High throughput true random number generator based on dynamically superimposed hybrid entropy sources

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yingchun Lu , Changlong Cao , Yang Liu , Huaguo Liang , Liang Yao , Lixiang Ma
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Abstract

True random number generator is a crucial hardware system component that is widely used in the fields of cryptographic communication, key generation, statistical simulation, and secure authentication. However, the related TRNG suffers from low throughput and high resource overhead due to relying on a single entropy source. To address this issue, a TRNG circuit implementation scheme based on a MUX-XOR gate cell (MX-cell) is proposed, which uses the switching characteristics of the MUX and the XOR gate to generate metastability and jitter to develop a hybrid entropy source. It further enables the dynamic superposition of entropy sources under prescribed conditions, which improves the TRNG throughput while reducing the resource overhead. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs with automatic placement and routing, passing NIST, AIS-31, TESTU01 statistical test suites and a series of other performance tests without post-processing. The experimental results reveal that the suggested design consumes only 19 LUTs, 8 DFFs, and 4 MUXs to provide random numbers with up to 380 Mbps throughput, which demonstrates highly efficient resource utilization compared to advanced published TRNGs.
基于动态叠加混合熵源的高吞吐量真随机数生成器
真随机数发生器是一个重要的硬件系统组件,广泛应用于加密通信、密钥生成、统计仿真和安全认证等领域。然而,相关的TRNG由于依赖单一熵源而存在低吞吐量和高资源开销的问题。针对这一问题,提出了一种基于MUX-XOR门单元(MX-cell)的TRNG电路实现方案,该方案利用MUX和XOR门的开关特性产生亚稳态和抖动,形成混合熵源。它进一步实现了在规定条件下熵源的动态叠加,提高了TRNG吞吐量,同时减少了资源开销。提出的TRNG在Xilinx Artix-7和Kintex-7 fpga上实现,具有自动放置和路由功能,通过NIST, AIS-31, TESTU01统计测试套件和一系列其他性能测试,无需后处理。实验结果表明,建议的设计仅消耗19个lut, 8个dff和4个mux来提供高达380 Mbps吞吐量的随机数,与先进的已发表的trng相比,这表明了高效的资源利用率。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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