Synchronous state judgment arbiter PUF circuit design based on FPGA

Abstract

The physical unclonable function (PUF) leverages the inherent randomness of hardware to generate unique identity identifiers or keys, offering a viable solution to the potential information leakage risks in internet of things (IoT) devices. However, the stability of PUFs can affect their practical application. In light of this, this paper proposes a high-stability arbiter PUF (APUF) circuit using a synchronous state judgment mechanism. Firstly, a path selection module is constructed using the two-to-one selector unit of the field programmable gate array (FPGA) as a random deviation source to generate signal delay differences. Then, a multi-arbiter judgment and mask error correction circuit is designed to detect and correct unstable response bits, enhancing the stability of the APUF. Finally, an experimental platform is built, and the test results show that the design not only significantly improves the stability of the APUF but also maintains good randomness and uniqueness.