{"title":"An improved TDM-based controller for a multilevel three-phase active frontend with variable DC ratios: The extended Negev rectifier","authors":"Eli Barbie, Dmitry Baimel","doi":"10.1016/j.aej.2025.01.128","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents an improved Time-Division-Multiplexing (TDM) based controller for a recently introduced multilevel three-phase (3ɸ) active frontend called the Negev rectifier. The new controller expands the Negev rectifier to attain a DC-link supply of either Equal DC Sources (EDCS) or Unequal DC Sources (UDCS) with variable DC ratios up to 1:5 while preserving the power factor correction functionality of the original Negev rectifier and reducing its switching frequency by more than 50 %. When validated as a frontend solution for UDCS-based MultiPoint Clamped (MPC) 3ɸ Multilevel Inverters (MLI), both staircase modulation and pulse-width modulation schemes are supported, achieving 16.3 % reduction in Line-voltage THD (LTHD) compared to conventional approaches. This allows UDCS-based voltage and current THD minimization, traditionally limited to cascaded H-bridge MLIs, to be adapted into AC-source-fed MLIs of the MPC topologies, better suited for 3ɸ applications. The Extended Negev Multilevel Rectifier (MLR) supports 3–8 output voltage levels (<em>N</em>). It eliminates MLI-side voltage balancing, making it suitable for various applications from low-voltage (400 V) aircraft systems to medium-voltage marine electrical distribution or any grid-fed MLR-MLI back-to-back power conversion system demanding high power quality. The controller was verified through comprehensive testing, including digital simulations, Processor-In-Loop (PIL) emulation, and Controller-Hardware-In-Loop (C-HIL) experiments across 4-, 5-, and 7-level configurations. Experimental results have revealed a current THD as low as 2.36 % with a voltage ripple of 1.2 % in a 4-level UDCS MLR configuration.</div></div>","PeriodicalId":7484,"journal":{"name":"alexandria engineering journal","volume":"119 ","pages":"Pages 359-378"},"PeriodicalIF":6.2000,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"alexandria engineering journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1110016825001553","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, MULTIDISCIPLINARY","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents an improved Time-Division-Multiplexing (TDM) based controller for a recently introduced multilevel three-phase (3ɸ) active frontend called the Negev rectifier. The new controller expands the Negev rectifier to attain a DC-link supply of either Equal DC Sources (EDCS) or Unequal DC Sources (UDCS) with variable DC ratios up to 1:5 while preserving the power factor correction functionality of the original Negev rectifier and reducing its switching frequency by more than 50 %. When validated as a frontend solution for UDCS-based MultiPoint Clamped (MPC) 3ɸ Multilevel Inverters (MLI), both staircase modulation and pulse-width modulation schemes are supported, achieving 16.3 % reduction in Line-voltage THD (LTHD) compared to conventional approaches. This allows UDCS-based voltage and current THD minimization, traditionally limited to cascaded H-bridge MLIs, to be adapted into AC-source-fed MLIs of the MPC topologies, better suited for 3ɸ applications. The Extended Negev Multilevel Rectifier (MLR) supports 3–8 output voltage levels (N). It eliminates MLI-side voltage balancing, making it suitable for various applications from low-voltage (400 V) aircraft systems to medium-voltage marine electrical distribution or any grid-fed MLR-MLI back-to-back power conversion system demanding high power quality. The controller was verified through comprehensive testing, including digital simulations, Processor-In-Loop (PIL) emulation, and Controller-Hardware-In-Loop (C-HIL) experiments across 4-, 5-, and 7-level configurations. Experimental results have revealed a current THD as low as 2.36 % with a voltage ripple of 1.2 % in a 4-level UDCS MLR configuration.
期刊介绍:
Alexandria Engineering Journal is an international journal devoted to publishing high quality papers in the field of engineering and applied science. Alexandria Engineering Journal is cited in the Engineering Information Services (EIS) and the Chemical Abstracts (CA). The papers published in Alexandria Engineering Journal are grouped into five sections, according to the following classification:
• Mechanical, Production, Marine and Textile Engineering
• Electrical Engineering, Computer Science and Nuclear Engineering
• Civil and Architecture Engineering
• Chemical Engineering and Applied Sciences
• Environmental Engineering