A 2b/cycle loop-unrolled SAR hybrid ADC with reused pre-amplifier technology

Abstract

A 2b/cycle loop-unrolled (LU) successive approximation register (SAR) hybrid analog-to-digital converter (ADC) is proposed for wireless communications applications. The proposed hybrid ADC expands the loop to enable the quantification of 2-bit within a single comparison cycle. Furthermore, the proposed design eliminates the reset time associated with the comparator, yielding an approximate 2.5$\times$ enhancement in the sampling rate. To overcome the offset mismatch and the corresponding calibration in the LU SAR ADC, the pre-amplifiers in the three-group comparators are reused, resulting in an improvement in signal-to-noise and distortion ratio (SNDR) of 5–6 dB. The proposed ADC is designed using a 180 nm CMOS process with a supply voltage of 1.8 V. Post-simulation results demonstrate that the proposed ADC achieves an SNDR of 59.13 dB with a power consumption of 3.39 mW, resulting in a Walden figure of merit of 45.85 fJ/conv.-step at a sampling rate of 100 MS/s and with a Nyquist input.