{"title":"An efficient ternary multiplier for enhanced on-chip AI wearable systems using graphene nanoribbon field-effect transistors","authors":"Jialing Li , Zhongjian Tang , Haitham A. Mahmoud","doi":"10.1016/j.aeue.2024.155658","DOIUrl":null,"url":null,"abstract":"<div><div>Enhanced on-chip AI wearable systems are transforming the interaction between individuals and technology, facilitating the development of smarter and more responsive devices that integrate seamlessly into everyday life. As the demand for such advanced systems increases, the necessity for energy-efficient circuits that provide extended battery life alongside high-performance processing becomes paramount. Within this framework, the graphene nanoribbon field-effect transistor (GNRFET) presents a promising solution, particularly due to its capability for ternary processing, which significantly enhances response speed, reduces power dissipation, and improves area efficiency.This paper presents an innovative ternary multiplier (TMUL) utilizing GNRFET technology, specifically designed to achieve reduced propagation delay, lower power consumption, and increased robustness against process variations, all while minimizing the transistor count. The proposed architecture incorporates a single transistor within the logic pathways leading to the outputs, integrates a greater number of high-threshold voltage (<em>V<sub>th</sub></em>) devices, and employs unary operators. These characteristics collectively advance the design objectives.The efficiency of the proposed TMUL is evaluated in comparison to seven contemporary TMUL circuits, employing a 32-nm GNRFET technology node with a supply voltage of 0.9 V. Remarkably, our design exhibits improvements of at least 8.98 % in delay, 2.22 % in power consumption, and 40.88 % in energy efficiency. Further performance assessment through Monte Carlo simulations confirms the superiority of the proposed design, underscoring its enhanced reliability amidst process variations and its minimal variance in energy consumption. By integrating the proposed single-trit TMUL to 3-trit TMUL, the projected circuit requires 1139 GNRFETs, with low power consumption and high speed operation.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155658"},"PeriodicalIF":3.0000,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Aeu-International Journal of Electronics and Communications","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1434841124005442","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Enhanced on-chip AI wearable systems are transforming the interaction between individuals and technology, facilitating the development of smarter and more responsive devices that integrate seamlessly into everyday life. As the demand for such advanced systems increases, the necessity for energy-efficient circuits that provide extended battery life alongside high-performance processing becomes paramount. Within this framework, the graphene nanoribbon field-effect transistor (GNRFET) presents a promising solution, particularly due to its capability for ternary processing, which significantly enhances response speed, reduces power dissipation, and improves area efficiency.This paper presents an innovative ternary multiplier (TMUL) utilizing GNRFET technology, specifically designed to achieve reduced propagation delay, lower power consumption, and increased robustness against process variations, all while minimizing the transistor count. The proposed architecture incorporates a single transistor within the logic pathways leading to the outputs, integrates a greater number of high-threshold voltage (Vth) devices, and employs unary operators. These characteristics collectively advance the design objectives.The efficiency of the proposed TMUL is evaluated in comparison to seven contemporary TMUL circuits, employing a 32-nm GNRFET technology node with a supply voltage of 0.9 V. Remarkably, our design exhibits improvements of at least 8.98 % in delay, 2.22 % in power consumption, and 40.88 % in energy efficiency. Further performance assessment through Monte Carlo simulations confirms the superiority of the proposed design, underscoring its enhanced reliability amidst process variations and its minimal variance in energy consumption. By integrating the proposed single-trit TMUL to 3-trit TMUL, the projected circuit requires 1139 GNRFETs, with low power consumption and high speed operation.
期刊介绍:
AEÜ is an international scientific journal which publishes both original works and invited tutorials. The journal''s scope covers all aspects of theory and design of circuits, systems and devices for electronics, signal processing, and communication, including:
signal and system theory, digital signal processing
network theory and circuit design
information theory, communication theory and techniques, modulation, source and channel coding
switching theory and techniques, communication protocols
optical communications
microwave theory and techniques, radar, sonar
antennas, wave propagation
AEÜ publishes full papers and letters with very short turn around time but a high standard review process. Review cycles are typically finished within twelve weeks by application of modern electronic communication facilities.