An 88 dB SNDR second-order CIFF delta-sigma modulator with 3-bit quantizer and capacitor sharing circuit

Abstract

A second-order cascaded-integrator feedforward integrator (CIFF) delta-sigma modulator (DSM) is proposed for sensor interfaces that require small area, low power, and high-resolution characteristics. It consists of two integrators containing capacitor arrays, a 3-bit quantizer based on a successive approximation register (SAR) analog-to-digital converter (ADC), and a data-weighted averaging (DWA) block. The proposed second-order CIFF DSM uses a three-bit quantizer instead of a single-bit quantizer to improve the dynamic characteristics of the DSM while reducing the area of the integration capacitors in the first integrator. In the second capacitor array used for the second integrator, a capacitor sharing circuit is implemented to perform the sampling for the second integrator, the summing for the CIFF, and the operation of the capacitor digital-to-analog converter (CDAC) for the SAR ADC-based 3-bit quantizer. The proposed capacitor sharing circuit reduces the area of the DSM for the sensor interface by eliminating the capacitors used for the summation of the CIFF and CDAC of the 3-bit quantizer. The proposed second-order CIFF DSM is designed using a 180-nm CMOS process, with an active area of 0.144 mm². It has a sampling rate of 125 kHz, using an external clock with a frequency of 750 kHz, and consumes 145.8 μW of power at a supply voltage of 1.8 V. When it has an oversampling ratio of 512, the measured SNDR for an input signal with a frequency of 100.0 Hz is approximately 88.4 dB.