CNTFET based leakage control static approximate full adder circuit for high performance multimedia applications

Abstract

The need for implementing fast and low-power digital circuits for high-performance multimedia applications running on portable devices demands major improvements in the design of full adder (FA) circuits, which form the fundamental building block of a digital system. In this work, a novel design of a FA circuit has been reported using a 32 nm CNTFET device to meet and improve the three design criteria of a FA, including speed, power consumption, and transistor count. Leveraging the benefits of approximate computing for multimedia applications, the proposed FA circuit has been implemented by modifying the 24-transitor conventional mirror adder circuit and using the leakage control transistor-based approach for minimizing the leakage power. This 11-transitor leakage control static approximate full adder (11T-LCSAFA) produces three erroneous outputs, and it has a power dissipation of 3.132 nW, propagation delay of 3.743 ps, and PDP of 11.72 x ${10}^{-21}$ J when operating at a voltage of 500 mV. Furthermore, the proposed 11T-LCSAFA has been used for implementing a 4-bit ripple carry adder (RCA) circuit to perform a multistage analysis. The implemented RCA has a maximum propagation delay of 39.929 ps, power dissipation of 23.37 nW, and PDP of 933 x ${10}^{-21}$ J.