Energy-efficient high-linearity SAR ADC with a unary–binary hybrid capacitor switching method

Abstract

This study developed a 10-bit 10 MS/s energy-efficient and high-linearity successive approximation register (SAR) analog-to-digital converter (ADC). The design utilized a capacitor array structure employing “3-bit thermometer code + 6-bit binary code” to achieve 10-bit quantization through a $V_{cm}$-based three-level capacitor switching scheme. The thermometer codes optimized the switching capacitors of the most significant bits to enhance linearity. Further, a unary and binary code control method was implemented to automatically switch across the remaining unary code capacitors when the differential output of the digital-to-analog converter was below 64 least significant bits (LSB). This method reduces the switching energy by 30% compared to the binary CDAC, while RMSDNL and RMSINL are reduced by 47.50% and 26.08%, respectively. The 10-bit SAR ADC was designed with $0.18\mu m$ CMOS technology, and the ADC core occupied an area of 0.077 mm${}^2$. At supply and reference voltages of 1.2 V, the ADC achieved differential non-linearity and integral non-linearity values of $+0.36/-0.32$ and $+0.4/-0.37$ LSB, respectively, at a sampling frequency of 10 MS/s and with a 1% capacitor mismatch. At an input signal frequency of 4.65 MHz, the ADC achieved a signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 60.07 and 80.03 dB, respectively. The ADC consumed a power of 137.36 $\mu$W, and the Walden figure of merit was 16.74 fJ/conversion-step.