Next-generation ferroelectric FETs: Modeling of recessed gate cylindrical junction less nanowire FETs for optimal electrostatic and linearity characteristics

Abstract

This study evaluates the performance of a recessed gate (Re-G) dielectric-engineered cylindrical junction less nanowire ferroelectric field-effect transistor (Re-G-CJNFe-FET) in comparison to a conventional cylindrical junction less nanowire ferroelectric field-effect transistor (CJNFe-FET). Introducing a Re-G design enhances the efficiency and overall device performance, achieving significant improvements in key metrics such as sub-threshold slope (SS), leakage current, transconductance (g_m), output conductance (g_d), and the Switching ratio (I_ON/I_OFF). The proposed device also shows superior performance in the transconductance generation function (TGF) and output conductance (g_d), early voltage (V_EA) while maintaining moderate linearity across parameters like second- and third-order harmonics, input intercept point (IIP₃), voltage intercept points (VIP₂, VIP₃), harmonic distortion (HD₂, HD₃), 1-db compression, and third-order intermodulation distortion (IMD₃). Simulation results obtained from the ATLAS 3-D simulator validate these findings, highlighting the potential of the Re-G-CJNFe-FET for analog applications and low power consumption in digital electronics.