Design and analysis of digital-like RF transmitter based on novel harmonic-rejected frequency multiplication architecture

Abstract

The increasing use of IoT technology highlights the importance of wireless sensing, where low power consumption and efficient transmission are critical. This paper presents a high-efficiency 400–460 MHz inductorless digital transmitter (TX) tailored for wireless sensing applications. The proposed design incorporates a novel harmonic-rejected frequency multiplication (HRFM) architecture to suppress 3rd- and 5th-order harmonics, ensuring efficient transmission with minimal power consumption. The architecture employs a delay-locked loop (DLL) and a resistance-divider-based edge combiner to both shape the output waveform for harmonic suppression and achieve 9x frequency multiplication. To further optimize DC power consumption, the HRFM generates multipath signals at lower frequencies through the DLL. A feedback-modified, highly matched charge pump (CP) with dynamic current compensation reduces CP charge/discharge current mismatch. Additionally, a dual voltage control approach enhances the operating range of the voltage-controlled delay line (VCDL). Implemented in a 65 nm CMOS process, the transmitter occupies a core area of 0.05 mm². Simulations show the DLL achieves a spur of approximately 61 dB, while post-layout simulations indicate harmonic distortions greater than −40 dBc for the 3rd-order and −52 dBc for the 5th-order harmonics, all without using inductors. The transmitter delivers −16 dBm output power to a 50 Ω antenna load, with a global DC power consumption of 1.3 mW. Overall, the proposed transmitter demonstrates highly efficient, low-power transmission for wireless sensing applications.