An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse

Abstract

Binary neural network (BNN) algorithms have gained significant attention due to their low computational complexity and improved accuracy. Field-programmable gate array (FPGA)-based accelerators for BNNs typically transform binary operations into XNOR and popcount operations, efficiently utilizing logic resources. However, fixed-point operations in the first and final layers result in high hardware costs. Moreover, frequent off-chip memory access, particularly for shortcut operations, can severely limit throughput.

This paper introduces a hardware-efficient FPGA-based BNN accelerator with minimized off-chip memory access. The first layer’s inputs are binarized using an enhanced thermometer encoding scheme, enabling all convolution layers to be executed on a unified binary computing unit. A multi-mode computing unit is designed to perform both ReAct parametric rectified linear unit (RPReLU) and linear operations using shared hardware multipliers, which maximizes hardware reuse. To address bandwidth limitations, we implement a dynamic data buffering architecture, featuring high-bandwidth and high-volume buffers for caching intra-layer and cross-layer data, respectively. The accelerator supports two data buffering schemes, and the one minimizing the off-chip memory access is selected for each convolution layer. The accelerator is evaluated on an Alinx AXU3EGB development board and a custom development board with a Xilinx XC7V690T device, respectively. Experiments on ImageNet demonstrate 69.34 % accuracy, with frames per second (FPS) of 129.1 and 405.6 on the ZU3EG and XC7V690T devices, respectively. Compared to the state-of-the-art design, our accelerator achieves 2.7$\times$ FPS on the same FPGA device.