Pengfei Ji , Chengyuan Liu , Li Dang , Shaoxuan Li , Ruixue Ding , Shubin Liu , Zhangming Zhu
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引用次数: 0
Abstract
This paper presents the design of a sampling network for an 8-bit, 16 GS/s, 16-channel time-interleaved analog-to-digital converter (ADC) implemented in a 28 nm CMOS process. The network is based on a two-stage resampling architecture. A current-feedback source follower is employed as the buffer, improving the speed and linearity of the buffering stages. Additionally, a novel parallel-path bootstrapped switch is introduced, which significantly enhances the sampling speed. The design also incorporates 4-phase, 4 GHz clocks for the first-stage switches and 16-phase, 1 GHz clocks for the second-stage switches. The entire sampling network occupies an area of 0.2 mm2 and consumes a total power of 63.95 mW. Post-simulation results demonstrate that the sampling network achieves a bandwidth exceeding 9 GHz, with a signal-to-noise plus distortion ratio (SNDR) of 57.6 dB and a spurious-free dynamic range (SFDR) of 62.1 dB at the Nyquist input frequency.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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