A simple interface circuit for edge inference kernels based on SC-LNO memristor crossbar

Abstract

Edge inference chips based on non-volatile memory hold promise in mitigating the bottleneck attributed to substantial data movement in artificial intelligence (AI) applications. Particularly, the efficient acceleration of numerous vector matrix multiply-accumulate (VMM) operations can be achieved through the collaboration of memristor crossbars and associated peripheral circuits. These efficient operations utilize the synaptic plasticity, high integration density, and inherent parallel execution capabilities of memristor crossbars. However, analog memristive devices often exhibit non-idealities such as readout nonlinearity, necessitating compatible peripheral interface circuits to ensure precision and stability in readout. In this work, a simple interface application-specified integrated circuit (ASIC) tailored to support non-ideal single-crystal $LiNb{O}_3$ (SC-LNO) memristor crossbars is proposed, facilitating the efficient realization of VMM operations. The transmit (TX) and receive (RX) components of the interface circuit are respectively responsible for stimulating and reading the outputs of the memristor crossbar. A common-mode voltage strategy is employed to avoid the I–V nonlinearity and negative voltage sensitivity inherent in memristors. The trans-impedance readout front end within the RX module ensures signal stability in the presence of large input parasitic capacitance. As a proof of concept, a 180-nm prototype ASIC is tested in conjunction with a resistor array featuring parallel parasitic capacitance, demonstrating its linearly stable readout capability. The entire interface circuit consumes a mere 2 mW, with the ASIC’s active area measuring 0.086 mm${}^2$.