The application of the optimized genetic algorithm in SerDes circuit design

Abstract

In modern high-speed communication systems, the main function of Serializer/Deserializer (SerDes) is to convert parallel data into high-speed serial data streams at the sending end to reduce the number and complexity of transmission lines. This study aims to solve the complex design problem of replacing inefficient, traditional parallel structures with high-speed serial interface SerDes. The Genetic Algorithm (GA) is optimized by adding a selection and substitution procedure, and the optimized GA is applied to the common-source amplifier. The low-frequency gain, bandwidth, and slew rate target circuit optimization design are completed. Additionally, the Clock and Data Recovery (CDR) circuit in SerDes is analyzed and designed. The CDR structure based on phase selector/phase interpolator type is used as the CDR circuit of the high-speed serial interface, enabling the final circuit function and performance to meet the requirements. Simulation experiments denote that the optimized GA can ensure that the evolved parameters allow the transistor to work in the saturation region to complete the common-drain amplifier's circuit optimization design. After 250 generations of evolution, the maximum gain of 0.75 is roughly achieved at an input voltage of 1.2V and a Metal Oxide Semiconductor (MOS) transistor width of 20 μm. The energy consumption per bit of data in the circuit based on the optimized GA is 16.8 pJ, 19.6 % lower than the 20.1 pJ of the conventional circuit before optimization. Therefore, the multi-objective circuit optimization design with a moderate gain is realized.