Design and implementation of a floating Pwell MTSCR for low-voltage ESD protection

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-02-01 DOI:10.1016/j.mejo.2024.106512

Fengfeng Zhou , Hongjiao Yang , Yang Wang , Jun Deng , Haotian Chen

引用次数: 0

Abstract

In order to improve the holding voltage (V_h) of low-voltage triggering silicon-controlled rectifier (LVTSCR), a cascade-MOS-embedded LVTSCR (MTSCR) and a floating Pwell MTSCR (FPMTSCR) are designed and manufactured based on a 0.18 μm CMOS process. In these two kinds of devices, MTSCR embeds a cascaded PMOS in traditional LVTSCR to form a surface shunting path to improve the holding voltage. FPMTSCR adds a narrow floating Pwell (PW2) in the drain region of the cascaded PMOS of MTSCR to further improve the holding voltage. The TLP and VF-TLP test results indicate that, compared to LVTSCR and MTSCR, FPMTSCR has higher holding voltage (V_h), higher holding current (I_h) and the high CDM robustness, and the low on-state resistance (R_on).

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.