Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations

Abstract

This work explores the impact of sheet thickness scaling on gate electrostatics of NsFETs using k.p simulation. It is shown that thin channel NsFETs exhibit higher threshold voltage irrespective of the substrate orientation and channel material. However, the influence of geometrical confinement varies among different substrate orientations and channel materials due to variations in carrier quantization mass. It is also shown that thin channel NsFETs deliver higher inversion charges at equivalent gate over-drive voltages, thereby offering enhanced gate electrostatics. However, the advantage of gate electrostatics in thin channel NsFETs is limited by quantum capacitance. Optimizing the sub-band structure through strategic selection of substrate orientations and channel materials is essential to regulate quantum capacitance and to fully exploit the benefits of sheet thickness scaling in NsFETs.