An 89-dB SNDR 50-kHz BW CT ZOOM ADC employing FIR DAC to enhance the ADC linearity

Abstract

This paper presents a CT Zoom ADC using a single-bit quantized first-order Sigma-Delta ADC as the coarse quantization ADC. The coarse quantization output is converted to be a multi-level output through a FIR filter, enhancing the ADC linearity and suppressing the sensitivity to clock jitter. Thus, not only can the designing difficulty be relieved, the power efficiency can be also improved. The fine-grained ADC adopts a third-order Sigma Delta ADC with single-bit quantization. The final output of the ZOOM ADC is the weighted average sum of the two-stage outputs.

In a 0.18 μm CMOS process, the circuit has achieved good performance. Within a bandwidth of 50 kHz, it achieves 89.3 dB SNDR, 14.5bits ENOB. The ADC core consumes 380 μW at a 1.8-V supply, resulting in a SNDR-based FoM of 170.5 dB. The size of the core ADC is 380μm × 520 μm.