A DTC-based fractional-N ADPLL using dual-core noise circulating DCO and loop bandwidth control techniques

Abstract

A fractional-N all digital phase locked loop (ADPLL) frequency synthesizer using loop bandwidth control technique is proposed in 65 nm CMOS. A lock detector gradually adjusts the loop bandwidth according to the state of the ADPLL to speed up the locking process and finally achieves accurate lock. A delta-sigma modulator (DSM) quantization noise cancellation technique which is based on a digital-to-time converter (DTC) is utilized to achieve lower fractional spurs, and a dual-core noise circulating digital controlled oscillator (DCO) is presented to achieve lower phase noise. According to the post-layout simulation results, the proposed ADPLL can operate properly at the frequency range of 12.0–15.0 GHz, with integrated jitter of 739 fs, reference spur of −80.3 dBc, fractional spur of −52.3 dBc, and power consumption of 36 mW.