Shrink eFPGA tile area by using custom cells and optimizing routing congestion

Abstract

—Embedded FPGA (eFPGA) is widely used in SoC design because of its process portability and flexible programmability. However, the area of eFPGA always occupies a larger area ratio, and due to the limitation of the number of available metal layers, it is easy to cause routing congestion and lead to a larger area. FPGA-specific custom cells can significantly reduce the total cell area of eFPGAs. When designing these custom cells, it's crucial to consider not only their compact implementation but also their interconnections with other cells to minimize routing congestion. Beyond customizing cells, optimizing the connections of configuration memory cells can further optimize routing congestion. This paper is dedicated to optimizing the physical implementation of eFPGA tiles. An eFPGA-specific custom cell design method with compact circuit structure is proposed to reduce the cell area while considering the routing connections. A more complete routing optimization method is proposed to completely optimize the connections of configuration memory cells to reduce routing congestion. We validated our approach in a 28 nm technology and found that our optimization can save 22.63 % in area while improving 33.89 % of worst case path delay compared with the standard cell implementation.