A dynamic comparator exploiting floating inverter preamplifier with stacked cross coupled feedback inverter for 16-bit 1 MS/s SAR ADC

Abstract

This paper presents a dynamic comparator based on floating inverter preamplifier (FIA) designed for high-resolution SAR ADCs. The comparator incorporates a floating inverter preamplifier with stacked cross-coupled feedback inverters and a latch. Load transistors are also added to the input transistors, enhancing small-signal gain and accelerating the initial integration speed of the FIA. The preamplifier achieves a higher gain, effectively suppressing input referred noise and accelerating the latch's regeneration process. Simulations performed using 180 nm CMOS technology with a 1.2 V supply demonstrate a significant gain increase, with only a minimal decrease in common-mode voltage, compared to state-of-the-art architectures. The simulation results indicate a pre-amplification stage gain of 52.9 dB, noise limited to 24 μV in tt corner, and energy consumption of 0.36 pJ per comparison, meeting the stringent requirements of a 16-bit SAR ADC. To validate its performance, the proposed comparator was implemented in a 16-bit 1 MS/s SAR ADC. Under transient noise conditions in post simulation, FFT results reveal a Signal-to-Noise and Distortion Ratio (SNDR) of 91.003 dB, confirming the comparator's enhanced capability to suppress input referred noise.